1. Field of the Invention
The present invention relate generally to semiconductor memory devices and in particular to a flash memory cell structure which having improved endurance to program/erase cycling.
2. Background Art
Flash semiconductor memories have recently been developed which are similar to conventional EPROMs in certain respects. However, unlike EPROMs which are programmed electrically and erased utilizing U.V. light, flash memories can be both electrically programmed and electrically erased.
Referring to the drawings, FIG. 1 depicts a conventional flash memory cell. The cell is formed in a P type substrate 10. An N+ source 12 and an N+ drain 14 are formed in the substrate 10. A channel region 16 is disposed in the substrate 10 intermediate the drain and source and adjacent the upper surface of the substrate.
A floating gate electrode 18, typically made of polysilicon, is disposed above the channel 16. A top or control gate 20, also typically made of polysilicon, is positioned above the channel 16 and the floating gate 20. A thin (about 100 .ANG.) gate oxide 22 separates the channel 16 from the floating gate 22. The floating gate 18 and top gate 20 are separated by an interpoly dielectric layer 24.
Programming the flash cell is similar to that of an EPROM. The source 12 is grounded, as is the substrate 10. An intermediate voltage is applied to the drain 14 and a high voltage is applied to the top gate 20. The intermediate drain voltage generates "hot" electrons that are swept across the channel 16. The "hot" electrons create additional free electrons in the channel 16. The electrons are attracted to the high voltage applied to the top gate 20. Some electrons from the channel cross the thin gate oxide 22 and enter the floating gate 20 where they are trapped. The trapped electrons alter the theshold voltage of the device. This phenomenon is widely described in the literature as "hot electron injection".
Erasure, i.e., discharge of the floating gate 20, is accomplished by grounding the top gate 20 (together with the substrate 10). The drain 14 is permitted to float and a high voltage is applied to the source 12. The high voltage at the source 12 develops a high electric field across the gate oxide 22 so as to pull electrons off of the floating gate 18 by way of a mechanism known as Fowler-Nordheim tunneling.
One shortcoming of the flash cell structure of FIG. 1 is that it is possible during the erase step to "over erase" the cell so that there is a net positive charge left on the floating gate 18. This positive charge will have a tendency to invert the P type channel 16 so as to form a conductive channel similar to that present in a depletion mode transistor. This conductive channel causes a small amount of current to be drawn through the cell even when the cell is supposed to be non-selected. In a typical memory array, a large number of cells are connected in parallel so that a relatively large amount of total current will be drawn thereby interfering with proper operation of the memory during the "read" operations.
FIG. 2 shows another embodiment of a memory cell of the type disclosed in U.S. Pat. No. 4,328,565. The cell includes a P type substrate 10, having an N+ source 12 and an N+ drain formed therein. A channel, designated by the numeral 16, is located between the source 12 and drain 14. A polysilicon floating gate 18 is positioned over a segment 16A of the channel 16 and at least the edge of the drain region 14. The floating gate 18 is spaced apart from the source region 12.
The FIG. 2 embodiment includes a top gate, generally designated by the numeral 20, which is positioned over the channel 16. Top gate 20, which is made of polysilicon, includes one segment 20A which is positioned over the floating gate 18/channel section 16A and another segment 20B which is positioned over the other channel section 16B. A gate oxide 22 is disposed between the floating gate 18 and the channel section 16A and an interpoly dielectric 24 is disposed between the top gate segment 20A and the floating gate 22.
U.S. Pat. No. 4,328,565 states that the FIG. 2 cell can be erased using U.V. light. In the alternative, the patent states that the gate oxide 22 can be provided with a thin region (50 .ANG.-150 .ANG.) so that a strong electric field can be applied across the oxide to induce Fowler-Nordheim tunneling.
Should the FIG. 2 cell structure be over erased as described in connection with the FIG. 1 embodiment, there will be a tendency to leave a net positive charge on the floating gate 18. As is the case with the FIG. 1 embodiment, this will have a tendency to induce a conduction path in channel 16 similar to that of a depletion mode transistor. However, the conduction path will be formed only in channel section 16A under the floating gate 22 and not in channel section 16B which is not affected by the charge on the floating gate. Since the two channel sections 16A and 16B are in series, there will be no leakage through channel 16 since section 16B cannot be converted to depletion mode.
Erasure of the FIG. 2 cell utilizing the Fowler-Nordheim tunneling mechanism can be accomplished by applying a negative voltage to the top gate 20 while grounding the source 12 (and the substrate 10). The drain 14 is left open so that Fowler-Nordheim tunneling through the gate oxide will take place.
It has been observed that above-described method of erasing the FIG. 2 cell structure can result in low program/erase cycle endurance. The drain 14 and substrate 10 are both maintained at zero volts so that it is possible that charges generated during both program and erase will be produced at the same point in the drain region. It is not possible to "erase" by applying a positive voltage to source region 12 since the source is spaced away from the floating gate 18.
It is known that it would be preferable to cause the injection of positive carriers during erase to take place over the full length of the channel 16 rather than the drain 14. However, this cannot be guaranteed since the drain and channel regions are maintained at the same voltage relative to the top gate voltage. Thus, it is possible that a significant number of carriers will be provided by the drain thereby reducing the program/erase cycle endurance of the device.
The present invention overcomes the above-noted shortcomings of the prior art memory cells. The advantages of the FIG. 2 cell are obtained, yet improved program/erase cycle endurance is achieved. These and other advantages of the subject invention will become apparent to those skilled in the art upon a reading of the following detailed description of the invention together with the drawings.